Single-Address-Space FaaS with Jord

Y. Li; A. Bhattacharyya; M. Kumar; A. Bhattacharjee; Yoav Etsion  et al.

Avant-Garde: Empowering GPUs with Scaled Numeric Formats

M. Gil; D. Ha; S. B. Harma; M. K. Yoon; B. Falsafi  et al.

Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox

S. Shrivastava; S. Tanaka; S. Nikolic; C. Ravishankar; D. Gaitonde  et al.

ROBoost: A Study of FPGA Logic-Based Power-Wasting Primitives

D. G. A. S. Mahmoud; S. Andreani; V. Lenders; M. Stojilovic

FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis

L. Coulon; L. Ramirez; J. Anderson; M. Stojilovic; P. Ienne

Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox

S. Shrivastava; S. Nicolic; S. Tanaka; C. Ravishankar; D. Gaitonde  et al.

ROBoost: A Study of FPGA Logic-Based Power-Wasting Primitives. Artifacts

D. G. A. S. Mahmoud; S. Andreani; V. Lenders; M. Stojilovic

MultiQueue-Based FPGA Routing: Relaxed A* Priority Ordering for Improved Parallelism

A. Singer; H. Yan; G. Zhang; M. Jeffrey; M. Stojilovic  et al.

Parallel FPGA Routing with On-the-Fly Net Decomposition

F. Kos; M. Stojilovic; V. Betz

UrbanTwin: An urban digital twin for climate action

D.-A. Constantinescu; V. Kartsch; Y. Nakatsuka; P. Wiese; P. Orbanovik  et al.

Electrical-Level Fault-Injection Attacks on FPGA-Based Systems

D. G. A. S. Mahmoud / B. Falsafi; M. Stojilovic (Dir.)

Server Architecture from Enterprise to Post-Moore

B. Falsafi; M. Ferdman; B. Grot

X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs

D. G. Mahmoud; B. Shokry; V. Lenders; W. Hu; M. Stojilović

Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs

D. G. Mahmoud; O. Glamočanin; F. Regazzoni; M. Stojilović

DOI : 10.1007/978-3-031-45395-3_5.

GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors

G. Zhou; M. Stojilovic; J. H. Anderson

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

S. Shrivastava; S. Nikolic; C. Ravishankar; D. Gaitonde; M. Stojilovic

What's Missing in Agile Hardware Design? Verification!

B. Falsafi

Scale-out Systolic Arrays

A. C. Yuzuguler; C. Sonmez; M. Drumond; Y. Oh; B. Falsafi  et al.

Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs

O. Glamocanin; H. Bazaz; M. Payer; M. Stojilovic

The Side-channel Metrics Cheat Sheet

K. Papagiannopoulos; O. Glamočanin; M. Azouaoui; D. Ros; F. Regazzoni  et al.

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

O. Glamočanin; S. Shrivastava; J. Yao; N. Ardo; M. Payer  et al.

Imprecise Store Exceptions

S. Gupta; Y. Li; Q. Kang; A. Bhattacharjee; B. Falsafi  et al.

RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks

D. Spielmann; O. Glamočanin; M. Stojilović

A Visionary Look at the Security of Reconfigurable Cloud Computing

M. Stojilović; K. Rasmussen; F. Regazzoni; M. B. Tahoori; R. Tessier

AstriFlash: A Flash-Based System for Online Services

S. Gupta; Y. Oh; L. Yan; M. J. Sutherland; A. Bhattacharjee  et al.

Active Wire Fences for Multitenant FPGAs

O. Glamocanin; A. Kostic; S. Kostic; M. Stojilovic

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

S. Shrivastava; S. Nikolic; C. Ravishankar; D. Gaitonde; M. Stojilovic

SecureCells: A Secure Compartmentalized Architecture

A. Bhattacharyya; F. Hofhammer; Y. Li; S. Gupta; A. Sánchez Marín  et al.

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

O. Glamocanin / B. Falsafi; M. Stojilovic (Dir.)

Rebooting Virtual Memory with Midgard

S. Gupta / B. Falsafi; A. Bhattacharjee (Dir.)

Cooperative Concurrency Control for Write-Intensive Key-Value Workloads

M. J. Sutherland; B. Falsafi; A. Daglis

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

D. G. A. S. Mahmoud; D. Dervishi; S. Hussein; V. Lenders; M. Stojilovic

A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time

H. Fendri; M. Macchetti; J. Perrine; M. Stojilovic

FPGA-to-CPU Undervolting Attacks

D. G. A. S. Mahmoud; S. Hussein; V. Lenders; M. Stojilovic

Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era

D. G. Mahmoud; V. Lenders; M. Stojilović

Deep Learning Detection of GPS Spoofing

O. Jullian; B. Otero; M. Stojilović; J. J. Costa; J. Verdú  et al.

Hardware and Software Support for RPC-Centric Server Architecture

M. J. Sutherland / B. Falsafi; A. Daglis (Dir.)

Equinox: Training (for Free) on a Custom Inference Accelerator

M. P. Drumond Lages De Oliveira; L. Coulon; A. Pourhabibi Zarandi; A. C. Yüzügüler; B. Falsafi  et al.

Cerebros: Evading the RPC Tax in Datacenters

A. Pourhabibi Zarandi; M. J. Sutherland; A. Daglis; B. Falsafi

Runtime Replacement of Machine Learning Modules in Fpga-based Systems

D. G. Mahmoud; B. Shokry; A. ElRefaey; H. H. Amer; I. Adly

NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs

M. B. Petersen; S. Nikolic; M. Stojilovic

Shared FPGAs and the Holy Grail: Protections against Side-Channel and Fault Attacks

O. Glamocanin; D. Mahmoud; F. Regazzoni; M. Stojilovic

Improving First-Order Threshold Implementations of SKINNY

A. F. Caforio; D. P. Collins; S. Banik; O. Glamocanin

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

Z. Seifoori; H. Asadi; M. Stojilovic

Data transformer apparatus

A. Pourhabibi Zarandi; S. Gupta; H. Kassir; M. Sutherland; Z. Tian  et al.

Rebooting Virtual Memory with Midgard

S. Gupta; A. Bhattacharyya; Y. Oh; A. Bhattacharjee; B. Falsafi  et al.

Hardware-Software Co-Design of an RPC Processor

A. Pourhabibi Zarandi / B. Falsafi (Dir.)

Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs

S. S. Mirzargar; G. Renault; A. Guerrieri; M. Stojilovic

Exploiting Errors for Efficiency: A Survey from Circuits to Applications

P. Stanley-Marbell; A. Alaghi; M. Carbin; E. Darulova; L. Dolecek  et al.

Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks?

O. Glamocanin; L. Coulon; F. Regazzoni; M. Stojilovic

Closing Leaks: Routing Against Crosstalk Side-Channel Attacks

Z. Seifoori; S. S. Mirzargar; M. Stojilovic

Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs

O. Glamocanin; L. Coulon; F. Regazzoni; M. Stojilovic

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

F. Gessler; P. Brisk; M. Stojilovic

X-Attack: Remote Activation of Satisfiability Don’t-Care Hardware Trojans on Shared FPGAs

D. Mahmoud; W. Hu; M. Stojilovic

ColTraIn: Co-located DNN training and inference

M. P. Drumond Lages De Oliveira / B. Falsafi; M. Jaggi (Dir.)

The NEBULA RPC-Optimized Architecture

M. Sutherland; S. Gupta; B. Falsafi; V. Marathe; D. Pnevmatikatos  et al.

Optimus Prime: Accelerating Data Transformation in Servers

A. Pourhabibi Zarandi; S. Gupta; H. Kassir; M. J. Sutherland; Z. Tian  et al.

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

J. Picorel; S. A. S. Kohroudi; Z. Yan; A. Bhattacharjee; B. Falsafi  et al.

A machine learning approach for power gating the FPGA routing network

S. Zeinab; H. Asadi; M. Stojilovic

Distributed Logless Atomic Durability with Persistent Memory

S. Gupta; A. Daglis; B. Falsafi

Physical Side-Channel Attacks and Covert Communication on FPGAs: A Survey

S. S. Mirzargar; M. Stojilovic

FPGA-Assisted Deterministic Routing for FPGAs

D. Korolija; M. Stojilovic

RPCValet: NI-Driven Tail-Aware Balancing of µs-Scale RPCs

A. Daglis; M. Sutherland; B. Falsafi

Mitigating Load Imbalance in Distributed Data Serving with Rack-Scale Memory Pooling

S. Novakovic; A. Daglis; D. Ustiugov; E. Bugnion; B. Falsafi  et al.

Timing Violation Induced Faults in Multi-Tenant FPGAs

D. Mahmoud; M. Stojilovic

SMoTherSpectre: Exploiting Speculative Execution through Port Contention

A. Bhattacharyya; A. Sandulescu; M. Neugschwandtner; A. Sorniotti; B. Falsafi  et al.

Analog Neural Networks with Deep-submicron Nonlinear Synapses

A. C. Yüzügüler; F. Çelik; M. P. Drumond Lages De Oliveira; B. Falsafi; P. Frossard

Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs

Y. Oh; G. Koo; M. Annavaram; W. W. Ro

Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores

A. Margaritov; S. Gupta; R. Gonzalez-Alberquilla; B. Grot

Design Guidelines for High-Performance SCM Hierarchies

D. Ustiugov; A. Daglis; J. Picorel Obando; M. J. Sutherland; E. Bugnion  et al.

Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model

Y. Moctar; M. Stojilovic; P. Brisk

LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching

M. Sadrosadati; A. Mirhosseini; S. B. Ehsani; H. Sarbazi-Azad; M. Drumond  et al.

Atomic object reads for in-memory rack-scale computing

A. Daglis; B. R. Grot; B. Falsafi

Towards Commoditizing Simulations of System Models Using Recurrent Neural Networks

A. C. Yuzuguler; A. Moga; C. Franke

Network-Compute Co-Design for Distributed In-Memory Computing

A. Daglis / B. Falsafi; E. Bugnion (Dir.)

Training DNNs with Hybrid Block Floating Point

M. Drumond; T. Lin; M. Jaggi; B. Falsafi

Unified prefetching into instruction cache and branch target buffer

B. Falsafi; I. C. Kaynak; B. R. Grot

Fat Caches For Scale-Out Servers

S. Volos; D. Jevdjic; B. Falsafi; B. Grot

The Mondrian Data Engine

M. P. Drumond Lages De Oliveira; A. Daglis; N. Mirzadeh; D. Ustiugov; J. Picorel Obando  et al.

FPGAs versus GPUs in Data centers

B. Falsafi; B. Dally; D. Singh; D. Chiou; J. J. Yi  et al.

Near-Memory Address Translation

J. Picorel Obando / B. Falsafi (Dir.)

Near-Memory Address Translation

J. Picorel; D. Jevdjic; B. Falsafi

Parallel FPGA routing: Survey and challenges

M. Stojilovic

A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction

H. Farbeh; N. S. Mirzadeh; N. F. Ghalaty; S.-G. Miremadi; M. Fazeli  et al.

Towards Near-Threshold Server Processors

A. Pahlevan; J. Picorel Obando; A. Pourhabibi Zarandi; D. Rossi; M. Zapater Sancho  et al.

The Case for RackOut: Scalable Data Serving Using Rack-Scale Systems

S. Novakovic; A. Daglis; E. Bugnion; B. Falsafi; B. Grot

Unlocking Energy

B. Falsafi; R. Guerraoui; J. Picorel Obando; V. Trigonakis

SABRes: Atomic Object Reads for In-Memory Rack-Scale Computing

A. Daglis; D. Ustiugov; S. Novakovic; E. Bugnion; B. Falsafi  et al.

Near-Memory Data Services

B. Falsafi; M. Stan; K. Skadron; N. Jayasena; Y. Chen  et al.

An Analysis of Load Imbalance in Scale-out Data Serving

S. Novakovic; A. Daglis; E. Bugnion; B. Falsafi; B. Grot

Multi-Gigabyte On-Chip DRAM Caches for Servers

D. Jevdic / B. Falsafi (Dir.)

Asynchronous memory access chaining

O. Kocberber; B. Falsafi; B. Grot

Sort vs. Hash Join Revisited for Near-Memory Execution

N. Mirzadeh; O. Kocberber; B. Falsafi; B. Grot

Shared Frontend for Manycore Server Processors

I. C. Kaynak / B. Falsafi; B. R. Grot (Dir.)

Sort vs. Hash Join Revisited for Near-Memory Execution

N. Mirzadeh; Y. O. Koçberber; B. Falsafi; B. Grot

Confluence: unified instruction supply for scale-out servers

C. Kaynak; B. Grot; B. Falsafi

Memory Systems and Interconnects for Scale-Out Servers

S. Volos / B. Falsafi (Dir.)

Accelerators for Data Processing

Y. O. Koçberber / B. Falsafi (Dir.)

Manycore Network Interfaces for In-Memory Rack-Scale Computing

A. Daglis; S. Novakovic; E. Bugnion; B. Falsafi; B. Grot

Big Data

B. Falsafi; B. Grot