Computation Is Fast, Use T<scp>hreadlet</scp>!: Efficient Threading for μs-Scale Computing via OS/Hardware Co-Design

Y. Yao; X. Qin; Y. Fan; Y. Li; K. Hu  et al.

Accurate & Scalable Time-Based Sampling of Full-System Simulation

S. Lin; Y. Li; M. Alian; B. Falsafi; K. Lai

Introduction to the FPL 2025 Journal Track

M. Stojilović; D. Stroobandt

Proceedings of the 16th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)

Introduction to the ARC 2025 Journal Track

R. Giorgi; M. Stojilovic

Power Breakdowns and PUE Implications of Air-Cooled and Direct-Liquid-Cooled Servers

A. Ning; X. E. Ouvrard; B. Falsafi

Design Space Exploration for Optimal Silicon-Efficient Server Chiplets

A. Chakraborty; A. Ansari; A. Ams; S. Lin; Y. Li  et al.

PathSteiner: Improving PathFinder with Quasi-Optimal Steiner-Tree Initialization

S. Shrivastava; L. Kurešević; A. Poupakis; C. Ravishankar; D. Gaitonde  et al.

AIPS: AI-Based Power Simulation for Pre-Silicon Side-Channel Security Evaluation

Y. Gao; H. Ma; T. ZHANG; J. He; Y. Zhao  et al.

PathSteiner: Improving PathFinder with Quasi-Optimal Steiner-Tree Initialization

S. Shrivastava; L. Kurešević; A. Poupakis; C. Ravishankar; D. Gaitonde  et al.

Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS

R. Pirayadi; A. Elakhras; M. Stojilovic; P. Ienne

Compressing DNNs Using Microscaling Formats with Sensitivity and Sparsity

S. B. Harma / B. Falsafi; M. Jaggi (Dir.)

Redesigning Hardware/Software Contracts for Modern Datacenter Systems

Y. Li / B. Falsafi (Dir.)

Accurate, Scalable, and Fast Time-Based Sampling of Full-System Simulation

S. Lin / B. Falsafi; M. Alian (Dir.)

From Monolithic to Multi-Stage Routing for FPGAs

S. Shrivastava / B. Falsafi; M. Stojilovic (Dir.)

Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS

R. Pirayadi; A. Elakhras; P. Ienne; M. Stojilovic

FRESCO: Efficient Subgraph Enumeration for Scalable Clustering in Heterogeneous CGRAs

L. Coulon; A. Ragab; J. Anderson; M. Stojilovic; P. Ienne

A Low-latency On-chip Cache Hierarchy for Load-to-use Stall Reduction in GPUs

N. (. (Nematollahi zadeh) Mahani; H. Falahati; S. Darabi; A. Javadi-Nezhad; Y. Oh  et al.

QFlex 3.0: Fast and Accurate ARM Server Simulation

S. Lin; A. Ansari; A. Chakraborty; B. Eryilmaz; Y. Li  et al.

Single-Address-Space FaaS with Jord

Y. Li; A. Bhattacharyya; M. Kumar; A. Bhattacharjee; Yoav Etsion  et al.

Avant-Garde: Empowering GPUs with Scaled Numeric Formats

M. Gil; D. Ha; S. B. Harma; M. K. Yoon; B. Falsafi  et al.

Constrained bit allocation for neural networks

S. Boudouh; S. B. Harma; A. Mahmoud; B. Falsafi

Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox

S. Shrivastava; S. Tanaka; S. Nikolic; C. Ravishankar; D. Gaitonde  et al.

ROBoost: A Study of FPGA Logic-Based Power-Wasting Primitives

D. G. A. S. Mahmoud; S. Andreani; V. Lenders; M. Stojilovic

Rethinking IOMMU for Future IO Devices

M. Kumar; Y. Li; Y. Etsion; A. Bhattacharjee; A. Basu  et al.

FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis

L. Coulon; L. Ramirez; J. Anderson; M. Stojilovic; P. Ienne

Effective Interplay Between Sparsity and Quantization: from Theory to Practice

S. B. Harma; A. Chakraborty; E. Kostenok; D. Mishin; D. Ha  et al.

Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox

S. Shrivastava; S. Nicolic; S. Tanaka; C. Ravishankar; D. Gaitonde  et al.

ROBoost: A Study of FPGA Logic-Based Power-Wasting Primitives. Artifacts

D. G. A. S. Mahmoud; S. Andreani; V. Lenders; M. Stojilovic

MultiQueue-Based FPGA Routing: Relaxed A* Priority Ordering for Improved Parallelism

A. Singer; H. Yan; G. Zhang; M. Jeffrey; M. Stojilovic  et al.

Parallel FPGA Routing with On-the-Fly Net Decomposition

F. Kos; M. Stojilovic; V. Betz

UrbanTwin: An urban digital twin for climate action

D.-A. Constantinescu; V. Kartsch; Y. Nakatsuka; P. Wiese; P. Orbanovik  et al.

Silicon Efficiency in Post-Moore Servers

A. Ansari; S. Lin; A. Chakraborty; M. Alian; B. Eryilmaz  et al.

X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs

D. G. Mahmoud; B. Shokry; V. Lenders; W. Hu; M. Stojilović

Electrical-Level Fault-Injection Attacks on FPGA-Based Systems

D. G. A. S. Mahmoud / B. Falsafi; M. Stojilovic (Dir.)

Server Architecture from Enterprise to Post-Moore

B. Falsafi; M. Ferdman; B. Grot

Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs

D. G. Mahmoud; O. Glamočanin; F. Regazzoni; M. Stojilović

DOI : 10.1007/978-3-031-45395-3_5.

GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors

G. Zhou; M. Stojilovic; J. H. Anderson

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

S. Shrivastava; S. Nikolic; C. Ravishankar; D. Gaitonde; M. Stojilovic

What's Missing in Agile Hardware Design? Verification!

B. Falsafi

Scale-out Systolic Arrays

A. C. Yuzuguler; C. Sonmez; M. Drumond; Y. Oh; B. Falsafi  et al.

Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs

O. Glamocanin; H. Bazaz; M. Payer; M. Stojilovic

The Side-channel Metrics Cheat Sheet

K. Papagiannopoulos; O. Glamočanin; M. Azouaoui; D. Ros; F. Regazzoni  et al.

Accuracy Boosters: Epoch-Driven Mixed-Mantissa Block Floating-Point for DNN Training

S. B. Harma; C. Sönmez; B. Falsafi; M. Jaggi; Y. Oh

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

S. Shrivastava; S. Nikolic; C. Ravishankar; D. Gaitonde; M. Stojilovic

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

O. Glamocanin / B. Falsafi; M. Stojilovic (Dir.)

Rebooting Virtual Memory with Midgard

S. Gupta / B. Falsafi; A. Bhattacharjee (Dir.)

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

O. Glamočanin; S. Shrivastava; J. Yao; N. Ardo; M. Payer  et al.

Active Wire Fences for Multitenant FPGAs

O. Glamocanin; A. Kostic; S. Kostic; M. Stojilovic

RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks

D. Spielmann; O. Glamočanin; M. Stojilović

A Visionary Look at the Security of Reconfigurable Cloud Computing

M. Stojilović; K. Rasmussen; F. Regazzoni; M. B. Tahoori; R. Tessier

Imprecise Store Exceptions

S. Gupta; Y. Li; Q. Kang; A. Bhattacharjee; B. Falsafi  et al.

Cooperative Concurrency Control for Write-Intensive Key-Value Workloads

M. J. Sutherland; B. Falsafi; A. Daglis

SecureCells: A Secure Compartmentalized Architecture

A. Bhattacharyya; F. Hofhammer; Y. Li; S. Gupta; A. Sánchez Marín  et al.

AstriFlash: A Flash-Based System for Online Services

S. Gupta; Y. Oh; L. Yan; M. J. Sutherland; A. Bhattacharjee  et al.

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

D. G. A. S. Mahmoud; D. Dervishi; S. Hussein; V. Lenders; M. Stojilovic

Accuracy Booster: Enabling 4-bit Fixed-point Arithmetic for DNN Training

S. B. Harma; A. Chakraborty; N. Sperry; B. Falsafi; M. Jaggi  et al.

A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time

H. Fendri; M. Macchetti; J. Perrine; M. Stojilovic

FPGA-to-CPU Undervolting Attacks

D. G. A. S. Mahmoud; S. Hussein; V. Lenders; M. Stojilovic

Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era

D. G. Mahmoud; V. Lenders; M. Stojilović

Deep Learning Detection of GPS Spoofing

O. Jullian; B. Otero; M. Stojilović; J. J. Costa; J. Verdú  et al.

Hardware and Software Support for RPC-Centric Server Architecture

M. J. Sutherland / B. Falsafi; A. Daglis (Dir.)

Equinox: Training (for Free) on a Custom Inference Accelerator

M. P. Drumond Lages De Oliveira; L. Coulon; A. Pourhabibi Zarandi; A. C. Yüzügüler; B. Falsafi  et al.

Cerebros: Evading the RPC Tax in Datacenters

A. Pourhabibi Zarandi; M. J. Sutherland; A. Daglis; B. Falsafi

Runtime Replacement of Machine Learning Modules in Fpga-based Systems

D. G. Mahmoud; B. Shokry; A. ElRefaey; H. H. Amer; I. Adly

NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs

M. B. Petersen; S. Nikolic; M. Stojilovic

Shared FPGAs and the Holy Grail: Protections against Side-Channel and Fault Attacks

O. Glamocanin; D. Mahmoud; F. Regazzoni; M. Stojilovic

Data transformer apparatus

A. Pourhabibi Zarandi; S. Gupta; H. Kassir; M. Sutherland; Z. Tian  et al.

Rebooting Virtual Memory with Midgard

S. Gupta; A. Bhattacharyya; Y. Oh; A. Bhattacharjee; B. Falsafi  et al.

Hardware-Software Co-Design of an RPC Processor

A. Pourhabibi Zarandi / B. Falsafi (Dir.)

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

Z. Seifoori; H. Asadi; M. Stojilovic

Improving First-Order Threshold Implementations of SKINNY

A. F. Caforio; D. P. Collins; S. Banik; O. Glamocanin

Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs

S. S. Mirzargar; G. Renault; A. Guerrieri; M. Stojilovic

Exploiting Errors for Efficiency: A Survey from Circuits to Applications

P. Stanley-Marbell; A. Alaghi; M. Carbin; E. Darulova; L. Dolecek  et al.

Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks?

O. Glamocanin; L. Coulon; F. Regazzoni; M. Stojilovic

Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs

O. Glamocanin; L. Coulon; F. Regazzoni; M. Stojilovic

Closing Leaks: Routing Against Crosstalk Side-Channel Attacks

Z. Seifoori; S. S. Mirzargar; M. Stojilovic

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

F. Gessler; P. Brisk; M. Stojilovic

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

J. Picorel; S. A. S. Kohroudi; Z. Yan; A. Bhattacharjee; B. Falsafi  et al.

ColTraIn: Co-located DNN training and inference

M. P. Drumond Lages De Oliveira / B. Falsafi; M. Jaggi (Dir.)

The NEBULA RPC-Optimized Architecture

M. Sutherland; S. Gupta; B. Falsafi; V. Marathe; D. Pnevmatikatos  et al.

AIPS: AI-Based Power Simulation for Pre-silicon Side-Channel Security Evaluation

Y. Gao; H. Ma; T. Zhang; j. He; Y. Zhao  et al.

X-Attack: Remote Activation of Satisfiability Don’t-Care Hardware Trojans on Shared FPGAs

D. Mahmoud; W. Hu; M. Stojilovic

Optimus Prime: Accelerating Data Transformation in Servers

A. Pourhabibi Zarandi; S. Gupta; H. Kassir; M. J. Sutherland; Z. Tian  et al.

A machine learning approach for power gating the FPGA routing network

S. Zeinab; H. Asadi; M. Stojilovic

Distributed Logless Atomic Durability with Persistent Memory

S. Gupta; A. Daglis; B. Falsafi

Physical Side-Channel Attacks and Covert Communication on FPGAs: A Survey

S. S. Mirzargar; M. Stojilovic

FPGA-Assisted Deterministic Routing for FPGAs

D. Korolija; M. Stojilovic

RPCValet: NI-Driven Tail-Aware Balancing of µs-Scale RPCs

A. Daglis; M. Sutherland; B. Falsafi

Mitigating Load Imbalance in Distributed Data Serving with Rack-Scale Memory Pooling

S. Novakovic; A. Daglis; D. Ustiugov; E. Bugnion; B. Falsafi  et al.

Timing Violation Induced Faults in Multi-Tenant FPGAs

D. Mahmoud; M. Stojilovic

Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs

Y. Oh; G. Koo; M. Annavaram; W. W. Ro

Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores

A. Margaritov; S. Gupta; R. Gonzalez-Alberquilla; B. Grot

SMoTherSpectre: Exploiting Speculative Execution through Port Contention

A. Bhattacharyya; A. Sandulescu; M. Neugschwandtner; A. Sorniotti; B. Falsafi  et al.

Analog Neural Networks with Deep-submicron Nonlinear Synapses

A. C. Yüzügüler; F. Çelik; M. P. Drumond Lages De Oliveira; B. Falsafi; P. Frossard

Design Guidelines for High-Performance SCM Hierarchies

D. Ustiugov; A. Daglis; J. Picorel Obando; M. J. Sutherland; E. Bugnion  et al.

Training DNNs with Hybrid Block Floating Point

M. Drumond; T. Lin; M. Jaggi; B. Falsafi

Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model

Y. Moctar; M. Stojilovic; P. Brisk

Network-Compute Co-Design for Distributed In-Memory Computing

A. Daglis / B. Falsafi; E. Bugnion (Dir.)

LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching

M. Sadrosadati; A. Mirhosseini; S. B. Ehsani; H. Sarbazi-Azad; M. Drumond  et al.