2026

Introduction to the FPL 2025 Journal Track

M. Stojilović; D. Stroobandt

ACM Transactions on Reconfigurable Technology and Systems. 2026. DOI : 10.1145/3844603.

AIPS: AI-Based Power Simulation for Pre-Silicon Side-Channel Security Evaluation

Y. Gao; H. Ma; T. ZHANG; J. He; Y. Zhao  et al.

IACR Transactions on Cryptographic Hardware and Embedded Systems. 2026. DOI : 10.46586/tches.v2026.i2.441-467.

2025

A Low-latency On-chip Cache Hierarchy for Load-to-use Stall Reduction in GPUs

N. (. (Nematollahi zadeh) Mahani; H. Falahati; S. Darabi; A. Javadi-Nezhad; Y. Oh  et al.

ACM Transactions on Architecture and Code Optimization. 2025. DOI : 10.1145/3760782.

2024

X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs

D. G. Mahmoud; B. Shokry; V. Lenders; W. Hu; M. Stojilović

IEEE Access. 2024. DOI : 10.1109/ACCESS.2024.3353134.

Server Architecture from Enterprise to Post-Moore

B. Falsafi; M. Ferdman; B. Grot

IEEE Micro. 2024. DOI : 10.1109/MM.2024.3418975.

2023

What's Missing in Agile Hardware Design? Verification!

B. Falsafi

Journal Of Computer Science And Technology. 2023. DOI : 10.1007/s11390-023-0005-3.

Scale-out Systolic Arrays

A. C. Yuzuguler; C. Sonmez; M. Drumond; Y. Oh; B. Falsafi  et al.

Acm Transactions On Architecture And Code Optimization. 2023. DOI : 10.1145/3572917.

The Side-channel Metrics Cheat Sheet

K. Papagiannopoulos; O. Glamočanin; M. Azouaoui; D. Ros; F. Regazzoni  et al.

ACM Computing Surveys. 2023. DOI : 10.1145/3565571.

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

O. Glamočanin; S. Shrivastava; J. Yao; N. Ardo; M. Payer  et al.

Journal of Hardware and Systems Security. 2023. DOI : 10.1007/s41635-023-00135-1.

RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks

D. Spielmann; O. Glamočanin; M. Stojilović

IACR Transactions on Cryptographic Hardware and Embedded Systems. 2023. DOI : 10.46586/tches.v2023.i2.543-567.

A Visionary Look at the Security of Reconfigurable Cloud Computing

M. Stojilović; K. Rasmussen; F. Regazzoni; M. B. Tahoori; R. Tessier

Proceedings of the IEEE. 2023. DOI : 10.1109/JPROC.2023.3330729.

2022

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

D. G. A. S. Mahmoud; D. Dervishi; S. Hussein; V. Lenders; M. Stojilovic

IEEE Access. 2022. DOI : 10.1109/ACCESS.2022.3231753.

Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era

D. G. Mahmoud; V. Lenders; M. Stojilović

ACM Computing Surveys. 2022. DOI : 10.1145/3498337.

2021

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

Z. Seifoori; H. Asadi; M. Stojilovic

IEEE Access. 2021. DOI : 10.1109/ACCESS.2021.3085005.

2020

Exploiting Errors for Efficiency: A Survey from Circuits to Applications

P. Stanley-Marbell; A. Alaghi; M. Carbin; E. Darulova; L. Dolecek  et al.

ACM Computing Surveys. 2020. DOI : 10.1145/3394898.

2019

Mitigating Load Imbalance in Distributed Data Serving with Rack-Scale Memory Pooling

S. Novakovic; A. Daglis; D. Ustiugov; E. Bugnion; B. Falsafi  et al.

ACM Transactions on Computer Systems. 2019. DOI : 10.1145/3309986.

Analog Neural Networks with Deep-submicron Nonlinear Synapses

A. C. Yüzügüler; F. Çelik; M. P. Drumond Lages De Oliveira; B. Falsafi; P. Frossard

IEEE Micro. 2019. DOI : 10.1109/MM.2019.2931182.

2017

FPGAs versus GPUs in Data centers

B. Falsafi; B. Dally; D. Singh; D. Chiou; J. J. Yi  et al.

IEEE Micro. 2017. DOI : 10.1109/MM.2017.19.

Fat Caches For Scale-Out Servers

S. Volos; D. Jevdjic; B. Falsafi; B. Grot

Ieee Micro. 2017. DOI : 10.1109/MM.2017.32.

2016

Near-Memory Data Services

B. Falsafi; M. Stan; K. Skadron; N. Jayasena; Y. Chen  et al.

IEEE Micro. 2016. DOI : 10.1109/MM.2016.9.

A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction

H. Farbeh; N. S. Mirzadeh; N. F. Ghalaty; S.-G. Miremadi; M. Fazeli  et al.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2016. DOI : 10.1109/TVLSI.2016.2544811.

2015

Asynchronous memory access chaining

O. Kocberber; B. Falsafi; B. Grot

Proceedings of the VLDB Endowment. 2015. DOI : 10.14778/2856318.2856321.

2014

Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip

H. Kim; B. Grot; P. V. Gratz; D. A. Jimenez

IEEE Transactions on Computers. 2014. DOI : 10.1109/Tc.2012.238.

A Case for Specialized Processors for Scale-Out Workloads

M. Ferdman; A. Adileh; O. Kocberber; S. Volos; M. Alisafaee  et al.

IEEE Micro. 2014. DOI : 10.1109/MM.2014.41.

Big Data

B. Falsafi; B. Grot

IEEE Micro. 2014. DOI : 10.1109/MM.2014.65.

2013

TOP PICKS FROM THE 2012 COMPUTER ARCHITECTURE CONFERENCES Introduction

B. Falsafi; G. H. Loh

IEEE Micro. 2013. DOI : 10.1109/MM.2013.65.

DeSyRe: On-demand system reliability

I. Sourdis; C. Strydis; A. Armato; C. S. Bouganis; B. Falsafi  et al.

Microprocessors and Microsystems - Embedded Hardware Design. 2013. DOI : 10.1016/j.micpro.2013.08.008.

2012

Clearing the clouds: a study of emerging scale-out workloads on modern hardware

M. Ferdman; A. Adileh; O. Kocberber; S. Volos; M. Alisafaee  et al.

ACM SIGARCH Computer Architecture News. 2012. DOI : 10.1145/2189750.2150982.

Quantifying the Mismatch between Emerging Scale-Out Applications and Modern Processors

M. Ferdman; A. Adileh; O. Kocberber; S. Volos; M. Alisafaee  et al.

ACM Transactions on Computer Systems. 2012. DOI : 10.1145/2382553.2382557.

Optimizing Data-Center TCO with Scale-Out Processors

B. Grot; D. Hardy; P. Lotfi-Kamran; B. Falsafi; C. Nicopoulos  et al.

IEEE Micro. 2012. DOI : 10.1109/MM.2012.71.

2011

Toward Dark Silicon in Servers

N. Hardavellas; M. Ferdman; B. Falsafi; A. Ailamaki

IEEE Micro. 2011. DOI : 10.1109/MM.2011.77.

2010

Reducing the Energy Dissipation of the Issue Queue by Exploiting Narrow Immediate Operands

C. Kaynak; O. Kocberber; O. Ergin

Journal of Circuits, Systems and Computers. 2010. DOI : 10.1142/S0218126610006992.

Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures

N. Hardavellas; M. Ferdman; B. Falsafi; A. Ailamaki

IEEE Micro. 2010. DOI : 10.1109/MM.2010.22.

Making Address-Correlated Prefetching Practical

T. F. Wenisch; M. Ferdman; A. Ailamaki; B. Falsafi; A. Moshovos

IEEE Micro. 2010. DOI : 10.1109/MM.2010.21.

2009

Flexible Hardware Acceleration for Instruction-Grain Lifeguards

S. Chen; M. Kozuch; P. B. Gibbons; M. Ryan; T. Strigkos  et al.

IEEE Micro Top Picks. 2009. DOI : 10.1109/MM.2009.6.

ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs

E. S. Chung; M. K. Papamichael; E. Nurvitadhi; J. C. Hoe; B. Falsafi  et al.

ACM Transactions on Reconfigurable Technology and Systems. 2009. DOI : 10.1145/1534916.1534925.

2008

Workshop on Transactional Computing (TRANSACT 2008) - Introduction

B. Falsafi; P. Felber

ACM SIGPLAN Notices. 2008. DOI : 10.1145/1402227.1402233.

2007

Low test application time resource binding for behavioral synthesis

M. Hosseinabady; P. Lotfi-Kamran; Z. Navabi

ACM Transactions on Design Automation of Electronic Systems. 2007. DOI : 10.1145/1230800.1230808.

Low Overhead DFT Using CDFG by Modifying Controller

M. Hosseinabady; P. Lotfi-Kamran; F. Lombardi; Z. Navabi

IET computers & digital techniques. 2007. DOI : 10.1049/iet-cdt:20050133.

2006

Coarse-grain coherence tracking: RegionScout and region coherence arrays

J. F. Cantin; J. E. Smith; M. H. Lipasti; A. Moshovos; B. Falsafi

IEEE Micro. 2006. DOI : 10.1109/MM.2006.8.

Dynamic feature selection for hardware prediction

A. Fern; R. Givan; B. Falsafi; T. N. Vijaykumar

Journal of Systems Architecture. 2006. DOI : 10.1016/j.sysarc.2004.12.007.

Statistical sampling of microarchitecture simulation

R. E. Wunderlich; T. F. Wenisch; B. Falsafi; J. C. Hoe

ACM Transactions on Modeling and Computer Simulation. 2006. DOI : 10.1145/1147224.1147225.

Exploiting reference idempotency to reduce speculative storage overflow

S. W. Kim; C.-L. Ooi; R. Eigenmann; B. Falsafi; T. N. Vijaykumar

ACM Transactions on Programming Languages and Systems. 2006. DOI : 10.1145/1152649.1152653.

2005

A case for asymmetric-cell cache memories

A. Moshovos; B. Falsafi; F. N. Najm; N. Azizi

IEEE Transactions on Very Large Scale Integration Systems. 2005. DOI : 10.1109/TVLSI.2005.850127.

TRUSS: A Reliable, Scalable Server Architecture

B. T. Gold; J. Kim; J. C. Smolens; E. Chung; V. Liaskovitis  et al.

IEEE Micro. 2005. DOI : 10.1109/MM.2005.122.

Evaluating scheduling policies for fine-grain communication protocols on a cluster of SMPs

B. Falsafi; D. A. Wood

Journal of Parallel and Distributed Computing. 2005. DOI : 10.1016/j.jpdc.2004.11.011.

2004

Fingerprinting: Bounding the Soft-Error Detection Latency and Bandwidth

J. C. Smolens; B. T. Gold; J. Kim; B. Falsafi; J. C. Hoe  et al.

IEEE Micro. 2004. DOI : 10.1109/MM.2004.72.

SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture

N. Hardavellas; S. Somogyi; T. F. Wenisch; R. E. Wunderlich; S. Chen  et al.

Performance Evaluation Review. 2004. DOI : 10.1145/1054907.1054914.

2003

Speculative Sequential Consistency with Little Custom Storage

C. Gniady; B. Falsafi

Journal of Instruction-Level Parallelism. 2003.

2002

Optimizing traffic in DSM clusters: fine-grain memory caching versus page migration/replication

A.-C. Lai; B. Falsafi

Theory of Computing Systems. 2002. DOI : 10.1007/s00224-002-1054-6.

2001

Reducing leakage in a high-performance deep-submicron instruction cache

M. D. Powell; S.-H. Yang; B. Falsafi; K. Roy; T. N. Vijaykumar

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2001. DOI : 10.1109/92.920821.

2000

Wisconsin Wind Tunnel II: a fast, portable parallel architecture simulator

S. S. Mukherjee; S. K. Reinhardt; B. Falsafi; M. Litzkow; M. D. Hill  et al.

IEEE Concurrency. 2000. DOI : 10.1109/4434.895100.

1999

Is SC + ILP = RC?

C. Gniady; B. Falsafi; T. N. Vijaykumar

ACM SIGARCH Computer Architecture News. 1999. DOI : 10.1145/307338.300993.

1997

Modeling cost/performance of a parallel computer simulator

B. Falsafi; D. A. Wood

ACM Transactions on Modeling and Computer Simulation. 1997. DOI : 10.1145/244804.244808.

1994

Mechanisms for Cooperative Shared Memory

D. A. Wood; S. Chandra; B. Falsafi; M. D. Hill; J. R. Larus  et al.

CMG Transactions. 1994. DOI : 10.1145/173682.165151.