CS 604 Advanced Topics on Memory Systems
Spring 2009

18-742 Paper Review Format

• Read the "Task of the Refree" by Alan Jay Smith posted on the Links page.
• Write a paragraph for each of the following:
  1. the context of the proposed research or design, the problem tackled (what was missing from prior work), and the proposed solution.
  2. list the key advantages of the proposed solution.
  3. list the key disadvantages.
  4. are there flaws in the methodology?

Reader 1: Cache Hierarchies
	(1)   Gurindar S. Sohi and Manoj Franklin, High-Bandwidth Data Memory Systems for Superscalar Processors
	(2)   Toni Juan, Juan J. Navarro, and Olivier Temam, Data Caches for Superscalar Processors
	(3)   Francois Bodin, Andre Seznec, Skewed associativity enhances performance predictability
	(4)   Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon Steely Jr., Joel Emer, Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching
	(5)   Bradford M. Beckmann, Michael R. Marty, and David A. Wood, ASR: Adaptive Selective Replication for CMP Caches
	(6)   Nikos Hardavellas, Michael Ferdman, Babak Falsafi, and Anastasia Ailamaki, R-NUCA: Data Placement in Distributed Shared Caches
	(7)   Bruce Jacob and Trevor Mudge, Virtual Memory: Issues of Implementation
	(8)   Bruce Jacob and Trevor Mudge, Virtual Memory in Contemporary Microprocessors
Reader 2: Prefetching
	(1)   An-Chow Lai, Cem Fide, and Babak Falsafi, Dead-Block Prediction & Dead-Block Correlating Prefetchers
	(2)   Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, and Andreas Moshovos, Temporal Streams in Commercial Server Applications
	(3)   Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, and Andreas Moshovos, Practical Off-chip Meta-data for Temporal Memory Streaming
	(4)   Stephen Somogyi, Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, and Andreas Moshovos, Spatial Memory Streaming
	(5)   Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N. Patt, Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors
	(6)   Kyle J. Nesbit and James E. Smith, Data Cache Prefetching Using a Global History Buffer
	(7)   Ilya Ganusov and Martin Burtscher, Efficient Emulation of Hardware Prefetchers via Event-Driven Helper Threading
Reader 3: DRAM systems
	(1)   Chang Joo Lee, Onur Mutlu, Veynu Narasiman, and Yale N. Patt, Prefetch-Aware DRAM Controllers
	(2)   Benjamin C. Lee, Engin Ipek, Onur Mutlu, and Doug Burger, Architecting Phase Change Memory as a Scalable DRAM Alternative
	(3)   Tom R. Halfhill, Z-RAM Shrinks Embedded Memory

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