Fast Parallel CAD for FPGAs

As transistor scaling is slowing down, other opportunities for ensuring continuous performance increase have to be explored. Field programmable gate arrays (FPGAs) are in the spotlight these days: not only due to their malleability and energy efficiency, but also because FPGAs have recently been integrated into the cloud. The latter makes them available to everyone in need of the immense computing power and data throughput they can offer. However, one important issue needs to be resolved first—the time to compile an industrial-scale design for an FPGA must be drastically reduced. Researchers have been looking for ways to accelerate FPGA compilation through parallelism. However, the ideal solution has not been found yet. This project addresses the said challenges by exploring new and effective strategies for software and hardware acceleration of the main computational bottlenecks: FPGA placement and routing.

S. Shrivastava, S. Nikolić, C. Ravishankar, D. Gaitonde, and M. Stojilović, IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Francisco, CA, USA, October 29 – November 2, 2023.
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S. Zeinab, H. Asadi, and M. Stojilović, Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing, IEEE Access, May 2021.
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M. B. Petersen, S. Nikolić, and M. Stojilović, NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs, International Symposium on Field-Programmable Gate Arrays, Virtual Conference, February 28 – March 2, 2021.
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F. Gessler, P. Brisk, and M. Stojilović, A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer, The 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems (VLSID), Bangalore, India, January 4 – 8, 2020.
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S. Zeinab, H. Asadi, and M. Stojilović, A Machine Learning Approach for Power Gating the FPGA Routing Network, 2019 International Conference on Field-Programmable Technology (ICFPT), Tianjin, China, December 9 – 13, 2019.
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D. Korolija and M. Stojilović, FPGA-Assisted Deterministic Routing for FPGAs, 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Rio de Janeiro, Brasil, May 20 – 24, 2019.
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Y. Moctar, M. Stojilović, and P. Brisk, Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model, The 28th International Conference on Field Programmable Logic and Applications (FPL), Dublin, IRELAND, August 26 – 31, 2018.
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M. Stojilović, Parallel FPGA routing: Survey and challenges, The 27th International Conference on Field Programmable Logic and Applications (FPL), Ghent, Belgium, September 4 – 8, 2017.
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