| Reader 1: Introduction |
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Chapter 6 (Sections 6.1 & 6.2) of Hennessy & Patterson's Computer Architecture |
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Smith, Alan Jay. The task of the referee. Computer 23.4 (1990) |
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| Reader 2: Project |
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Platt, John R. Strong Inference: Certain systematic methods of scientific thinking may produce much more rapid progress than others. science 146.3642 (1964) |
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| Reader 3: Evaluation |
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Gupta, Udit, et al. Chasing carbon: The elusive environmental footprint of computing |
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Wunderlich, Roland E., et al. SMARTS: Accelerating microarchitecture simulation via rigorous statistical sampling. |
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| Reader 4: Parallel Software Construction I |
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Chapter 1.2 of Culler, D., Singh, J. P., & Gupta, A. (1999). Parallel computer architecture: a hardware/software approach. |
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| Reader 5: Parallel Software Construction II |
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Paszke, Adam, et al. Pytorch: An imperative style, high-performance deep learning library. |
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Birrell, Andrew D., and Bruce Jay Nelson. Implementing remote procedure calls |
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| Reader 6: Coherence |
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Background: Chapter 6 and 7 of Nagarajan, Sorin, Hill, Wood's A Primer on Memory Consistency and Cache Coherence |
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Background slides from CS-307 regarding coherence |
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Moshovos, Andreas, et al. JETTY: Filtering snoops for reduced energy consumption in SMP servers |
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Ferdman, Michael, et al. Cuckoo directory: A scalable directory for many-core systems |
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| Reader 7: Memory Ordering |
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Background slides from CS-307 regarding hardware memory reordering |
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Background slides from CS-307 regarding compiler memory reordering |
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Adve, Sarita V., and Kourosh Gharachorloo. Shared memory consistency models: A tutorial |
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Blundell, Colin, Milo MK Martin, and Thomas F. Wenisch. Invisifence: performance-transparent memory ordering in conventional multiprocessors |
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| Reader 8: Manycore Caches |
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Chapter 2 of Balasubramonian, Jouppi & Muralimanohar's Multi-Core Cache Hierarchies |
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Xie, Yuejian, and Gabriel H. Loh. PIPP: Promotion/insertion pseudo-partitioning of multi-core shared caches |
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Hardavellas, Nikos, et al. Reactive NUCA: near-optimal block placement and replication in distributed caches |
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| Reader 9: GPU and Multithreading |
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Background slides from CS307 regarding GPU introduction |
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Background slides from CS307 regarding GPU programming |
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Chapter 1 and 2 of Nemirovsky & Tullsen's Multithreading architecture |
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Choquette, Jack. Nvidia hopper h100 gpu: Scaling performance |
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| Reader 10: Interconnect I |
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Appendix F of Hennessy & Patterson's Computer Architecture |
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| Reader 11: Interconnect II |
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Chapter 6 of Jerger & Peh's On-Chip Networks |
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| Reader 12: DRAM Caches |
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Volos, Stavros, et al. Fat caches for scale-out servers |
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Sodani, Avinash, et al. Knights landing: Second-generation Intel XEON Phi product |
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| Reader 13: Workload I |
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Ferdman, Michael, et al. Clearing the clouds: a study of emerging scale-out workloads on modern hardware |
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Gan, Yu, et al. An open-source benchmark suite for microservices and their hardware-software implications for cloud & edge systems |
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| Reader 14: Workload II |
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Ustiugov, Dmitrii, et al. Benchmarking, analysis, and optimization of serverless function snapshots |
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Reddi, Vijay Janapa, et al. Mlperf inference benchmark |
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| Reader 15: Servers |
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Dean, Jeffrey, and Luiz André Barroso. The tail at scale. |
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Barroso, Luiz, et al. Attack of the killer microseconds. |
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| Reader 16: Cloud-Native CPUs |
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Lotfi-Kamran, Pejman, et al. Scale-out processors |
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Lotfi-Kamran, Pejman, Boris Grot, and Babak Falsafi. NOC-Out: Microarchitecting a scale-out processor |
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| Reader 17: Cloud-Native Acclerators |
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Biswas, Arijit, and Sailesh Kottapalli. Next-Gen Intel Xeon CPU-Sapphire Rapids |
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Kocberber, Onur, et al. Meet the walkers: Accelerating index traversals for in-memory databases |
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| Reader 18: AI Acclerators |
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Jouppi, Norman P., et al. Ten lessons from three generations shaped google's tpuv4i |
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Drumond, Mario, et al. Equinox: Training (for free) on a custom inference accelerator |
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| Reader 19: Near-Memory Computing |
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Drumond, Mario, et al. The mondrian data engine |
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Aga, Shaizeen, Supreet Jeloka, Arun Subramaniyan, Satish Narayanasamy, David Blaauw, and Reetuparna Das. Compute caches. |
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| Reader 20: Cloud-Native Memory I |
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Li, Huaicheng, et al. Pond: CXL-based memory pooling systems for cloud platforms |
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Ousterhout, John, et al. The case for RAMClouds: scalable high-performance storage entirely in DRAM. |
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| Reader 21: Cloud-Native Memory II |
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Gupta, Siddharth, et al. Rebooting virtual memory with Midgard |
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Bhattacharyya, Atri, et al. Securecells: A secure compartmentalized architecture. |
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| Reader 22: Cloud-Native Networks I |
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Daglis, Alexandros, Mark Sutherland, and Babak Falsafi. RPCValet: NI-driven tail-aware balancing of µs-scale RPCs |
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Sutherland, Mark, et al. The NeBuLa RPC-optimized architecture |
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| Reader 23: Cloud-Native Networks II |
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Karandikar, Sagar, et al. A hardware accelerator for protocol buffers. |
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Pourhabibi, Arash, et al. Cerebros: Evading the rpc tax in datacenters |
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| Reader 24: Datacenters |
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Chapter 1 and 2 of Barroso & Hölzle's The Datacenter as a Computer - An Introduction to the Design of Warehouse-Scale Machines |
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