M. Stojilović, K. Rasmussen, F. Regazzoni, M. Tahoori, and R. Tessier, A Visionary Look at the Security of Reconfigurable Cloud Computing, Proceedings of the IEEE, December 2023
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D. G. Mahmoud, O. Glamočanin, F. Regazzoni, and M. Stojilović, Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs, (eds) Security of FPGA-Accelerated Cloud Computing Environments. Springer, Cham. September, 2023
O. Glamočanin, A. Kostić, S. Kostić, and M. Stojilović, Active Wire Fences for Multitenant FPGAs, 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Tallinn, Estonia, May 3 – 5, 2023, Best Paper Award Nominee.
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O. Glamočanin, H. Bazaz, M. Payer, and M. Stojilović, Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs, Design, Automation and Test in Europe Conference DATE 2023, Antwerp, Belgium, April 17 – 19, 2023.
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K. Papagiannopoulos, O. Glamočanin, M. Azouaoui, D. Ros, F. Regazzoni, and M. Stojilović, The Side-Channel Metrics Cheat Sheat, ACM Computing Surveys, vol. 55, issue 10, Feb 2, 2023.
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D. Spielmann, O. Glamočanin, and M. Stojilović, RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks, Conference on Cryptographic Hardware and Embedded Systems (CHES), Praque, Czechia, September 10 – 14, 2023.
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O. Glamočanin, D. G. Mahmoud, F. Regazzoni, and M. Stojilović, Shared FPGAs and the Holy Grail: Protections against Side-Channel and Fault Attacks, Design, Automation and Test in Europe Conference and Exhibition (DATE), Virtual Conference and Exhibition, February 1 – 5, 2021.
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S. S. Mirzargar, G. Renault, A. Guerrieri and M. Stojilović, Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs, Cryptology ePrint Archive, November 29, 2020.
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S. S. Mirzargar, G. Renault, A. Guerrieri and M. Stojilović, Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs, International Conference on Field-Programmable Technology, Maui, HI, USA (Virtual conference), December 9 – 11, 2020.
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O. Glamočanin, L. Coulon, F. Regazzoni, and M. Stojilović, Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks?, Design, Automation and Test in Europe Conference and Exhibition (DATE), Grenoble, France, March 9 – 13, 2020.
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O. Glamočanin, L. Coulon, F. Regazzoni, and M. Stojilović, Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs, The 28th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2020), Seaside, California, USA, February 23 – 25, 2020.
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Z. Seifoori, S. S. Mirzargar, and M. Stojilović, Closing Leaks: Routing Against Crosstalk Side-Channel Attacks, The 28th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2020), Seaside, California, USA, February 23 – 25, 2020.
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S. S. Mirzargar and M. Stojilović, Physical Side-Channel Attacks and Covert Communication on FPGAs: A Survey, The 29th International Conference on Field Programmable Logic and Applications (FPL), Barcelona, Spain, September 9 – 13, 2019.
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D. Mahmoud and M. Stojilović, Timing Violation Induced Faults in Multi-Tenant FPGAs, Design, Automation and Test in Europe Conference and Exhibition (DATE), Florence, Italy, March 25 – 29, 2019.
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