Publications
| Conference Papers | Journal Papers | Technical Reports | Ph.D. Theses | Book chapters | Books |
2024
X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs
IEEE Access. 2024. DOI : 10.1109/ACCESS.2024.3353134.2023
What's Missing in Agile Hardware Design? Verification!
Journal Of Computer Science And Technology. 2023-07-01. DOI : 10.1007/s11390-023-0005-3.Scale-out Systolic Arrays
Acm Transactions On Architecture And Code Optimization. 2023-06-01. DOI : 10.1145/3572917.The Side-channel Metrics Cheat Sheet
ACM Computing Surveys. 2023-02-02. DOI : 10.1145/3565571.A Visionary Look at the Security of Reconfigurable Cloud Computing
Proceedings of the IEEE. 2023. DOI : 10.1109/JPROC.2023.3330729.Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs
Journal of Hardware and Systems Security. 2023. DOI : 10.1007/s41635-023-00135-1.RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks
IACR Transactions on Cryptographic Hardware and Embedded Systems. 2023. DOI : 10.46586/tches.v2023.i2.543-567.2022
DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks
IEEE Access. 2022-12-22. DOI : 10.1109/ACCESS.2022.3231753.Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era
ACM Computing Surveys. 2022-02-03. DOI : 10.1145/3498337.2021
Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing
IEEE Access. 2021. DOI : 10.1109/ACCESS.2021.3085005.2020
Exploiting Errors for Efficiency: A Survey from Circuits to Applications
Acm Computing Surveys. 2020-06-01. DOI : 10.1145/3394898.2019
Mitigating Load Imbalance in Distributed Data Serving with Rack-Scale Memory Pooling
ACM Transactions on Computer Systems. 2019-04-01. DOI : 10.1145/3309986.Analog Neural Networks with Deep-submicron Nonlinear Synapses
IEEE Micro. 2019. DOI : 10.1109/MM.2019.2931182.2017
Fat Caches For Scale-Out Servers
Ieee Micro. 2017. DOI : 10.1109/MM.2017.32.FPGAs versus GPUs in Data centers
IEEE Micro. 2017. DOI : 10.1109/MM.2017.19.2016
A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2016. DOI : 10.1109/TVLSI.2016.2544811.Near-Memory Data Services
IEEE Micro. 2016. DOI : 10.1109/MM.2016.9.2015
Asynchronous memory access chaining
Proceedings of the VLDB Endowment. 2015. DOI : 10.14778/2856318.2856321.2014
Big Data
IEEE Micro. 2014. DOI : 10.1109/MM.2014.65.A Case for Specialized Processors for Scale-Out Workloads
IEEE Micro. 2014. DOI : 10.1109/MM.2014.41.Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip
IEEE Transactions on Computers. 2014. DOI : 10.1109/Tc.2012.238.2013
DeSyRe: On-demand system reliability
Microprocessors and Microsystems - Embedded Hardware Design. 2013. DOI : 10.1016/j.micpro.2013.08.008.TOP PICKS FROM THE 2012 COMPUTER ARCHITECTURE CONFERENCES Introduction
IEEE Micro. 2013. DOI : 10.1109/MM.2013.65.2012
Quantifying the Mismatch between Emerging Scale-Out Applications and Modern Processors
ACM Transactions on Computer Systems. 2012. DOI : 10.1145/2382553.2382557.Optimizing Data-Center TCO with Scale-Out Processors
IEEE Micro. 2012. DOI : 10.1109/MM.2012.71.2011
Toward Dark Silicon in Servers
IEEE Micro. 2011. DOI : 10.1109/MM.2011.77.2010
Reducing the Energy Dissipation of the Issue Queue by Exploiting Narrow Immediate Operands
Journal of Circuits, Systems and Computers. 2010. DOI : 10.1142/S0218126610006992.Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures
IEEE Micro. 2010. DOI : 10.1109/MM.2010.22.Making Address-Correlated Prefetching Practical
IEEE Micro. 2010. DOI : 10.1109/MM.2010.21.2009
Flexible Hardware Acceleration for Instruction-Grain Lifeguards
IEEE Micro Top Picks. 2009. DOI : 10.1109/MM.2009.6.ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs
ACM Transactions on Reconfigurable Technology and Systems. 2009. DOI : 10.1145/1534916.1534925.2008
Workshop on Transactional Computing (TRANSACT 2008) - Introduction
Acm Sigplan Notices. 2008. DOI : 10.1145/1402227.1402233.2007
Low test application time resource binding for behavioral synthesis
ACM Transactions on Design Automation of Electronic Systems. 2007. DOI : 10.1145/1230800.1230808.Low Overhead DFT Using CDFG by Modifying Controller
IET computers & digital techniques. 2007. DOI : 10.1049/iet-cdt:20050133.2006
Statistical sampling of microarchitecture simulation
ACM Transactions on Modeling and Computer Simulation. 2006. DOI : 10.1145/1147224.1147225.Exploiting reference idempotency to reduce speculative storage overflow
ACM Transactions on Programming Languages and Systems. 2006. DOI : 10.1145/1152649.1152653.Dynamic feature selection for hardware prediction
Journal of Systems Architecture. 2006. DOI : 10.1016/j.sysarc.2004.12.007.Coarse-grain coherence tracking: RegionScout and region coherence arrays
IEEE Micro. 2006. DOI : 10.1109/MM.2006.8.SimFlex: Statistical Sampling of Computer System Simulation
IEEE Micro. 2006. DOI : 10.1109/MM.2006.79.2005
A case for asymmetric-cell cache memories
IEEE Transactions on Very Large Scale Integration Systems. 2005. DOI : 10.1109/TVLSI.2005.850127.Evaluating scheduling policies for fine-grain communication protocols on a cluster of SMPs
Journal of Parallel and Distributed Computing. 2005. DOI : 10.1016/j.jpdc.2004.11.011.TRUSS: A Reliable, Scalable Server Architecture
IEEE Micro. 2005. DOI : 10.1109/MM.2005.122.2004
SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture
Performance Evaluation Review. 2004. DOI : 10.1145/1054907.1054914.Fingerprinting: Bounding the Soft-Error Detection Latency and Bandwidth
IEEE Micro. 2004. DOI : 10.1109/MM.2004.72.2003
Speculative Sequential Consistency with Little Custom Storage
Journal of Instruction-Level Parallelism. 2003.2002
Optimizing traffic in DSM clusters: fine-grain memory caching versus page migration/replication
Theory of Computing Systems. 2002. DOI : 10.1007/s00224-002-1054-6.2001
Reducing leakage in a high-performance deep-submicron instruction cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2001. DOI : 10.1109/92.920821.2000
Wisconsin Wind Tunnel II: a fast, portable parallel architecture simulator
IEEE Concurrency. 2000. DOI : 10.1109/4434.895100.1999
Is SC + ILP = RC?
ACM SIGARCH Computer Architecture News. 1999. DOI : 10.1145/307338.300993.1997
Modeling cost/performance of a parallel computer simulator
ACM Transactions on Modeling and Computer Simulation. 1997. DOI : 10.1145/244804.244808.1994
Mechanisms for Cooperative Shared Memory
CMG Transactions. 1994. DOI : 10.1145/173682.165151.BibTex for all references found